Configuration of the GMT (preliminary)

The GMT is configurable by changing registers and look-up-tables (LUTs). Both are accessible via the VME bus.

GMT Look-Up-Tables

Location	LUT name	inputs	outputs
MIAU FPGA	MIAUEtaConvLUT	eta_in	eta_red
	MIAUPhiPro1LUT	eta_red, phi, pt, ch	phi_calo_fine, phi_calo_ofs
	MIAUPhiPro2LUT	phi, phi_calo_fine, phi_calo_ofs, ch	phi_select_bits
	MIAUEtaProLUT	eta_in, pt, ch	eta_select_bits
Logic FPGA	LFSortRankEtaQLUT	eta_in, q	srk_etaq, very_low_q
	LFSortRankPtQLUT	pt, q	srk_ptq
	LFSortRankEtaPhiLUT	eta_in, phi	srk_etaphi / disable_hot
	LFSortRankCombineLUT	srk_etaq, srk_ptq, srk_etaphi	sort_rank
	LFDeltaEtaLUT	eta_in, eta_in	delta_eta
	LFOvlEtaConvLUT	eta_in	eta_ovl
	LFCOUDeltaEtaLUT	eta_ovl, eta_ovl	delta_eta
	LFMatchQualLUT	delta_eta, delta_phi	match_qual
	LFEtaConvLUT	eta_in	eta_gmt
	LFMergeRankEtaQLUT	eta_in, q	mrk_etaq, merge_method
	LFMergeRankPtQLUT	pt, q	mrk_ptq
	LFMergeRankEtaPhiLUT	eta_in, phi	mrk_etaphi
	LFMergeRankCombineLUT	srk_etaq, srk_ptq, srk_etaphi	merge_rank
	LFPtMixLUT	pt, pt	pt
	LFDisableHotLUT	eta_in, phi	disable hot
	LFPhiProEtaConvLUT	eta_in	eta_red
	LFPhiProLUT	eta_red, pt, ch	delta_phi

signal	bits	meaning
eta_in	6	input eta in regioanl trigger scale
phi	8	Phi
pt	5	Pt code
ch	1	charge (0=pos, 1=neg)
q	3	quality in regional trigger scale
eta_red	4	reduced resolution eta scale
phi_calo_fine	1	fine projected phi in 1/2 calo regions
phi_calo_ofs	3	projected phi ofset in calo regions
phi_select_bits	18	selected calo regiosn in phi
eta_select_bits	10	selected calo regions in eta

srk_etaq	2	sort rank contribution based on eta and quality
vey_low_q	2	very low quality code
srk_ptq	7	sort rank contribution based on pt and quality
srk_etaphi	2	sort rank contribution based on eta and phi (code 3 = disable region)
srk	8	sort rank of muon
delta_eta	4	delta eta
eta_ovl	4	reduced resolution eta scale for overlap region
delta_phi	3	delta-phi
match_qual	6	match quality
mrk_etaq	7	merge rank contribution based on eta and quality
merge_method	1	flag to selcet merge method when combined merging is selected
mrk_ptq	2	merge rank contribution based on pt and quality
mrk_etaphi	1	merge rank contribution based on eta and phi
merge_rank	8	merge rank of a muon
eta_gmt	6	eta in GMT output scale

Location	LUT name	inputs	outputs	bits in	bits out	RAM Type * (# blks)	bits VME addr	bits VME data	VME size per instance (bytes)	instances per chip	RAM Blocks per chip	VME base address in chip
MIAU FPGA	MIAUEtaConvLUT	eta_in	eta_red	6	4	D	6	4	128	16	-	0x400
	MIAUPhiPro1LUT	eta_red, phi, pt, ch	phi_calo_fine, phi_calo_ofs	13	4	B(2)	11	16	4096	16	32	0x10000
	MIAUPhiPro2LUT	phi, phi_calo_fine, phi_calo_ofs, ch	phi_select_bits	10	18	B(1)	11	9	4096	16	16	0x20000
	MIAUEtaProLUT	eta_in, pt, ch	eta_select_bits	12	10	B(3)	12	10	8192	16	48	0x30000
Logic FPGA	LFMatchQualLUT	delta_eta, delta_phi	match_qual	7	6	D	7	6	256	48	-	0x0400
	LFCOUDeltaEta	eta_ovl, eta_ovl	delta_eta	8	4	D	8	4	512	32	-	0x3400
	OvlEtaConvLUT	eta_in	eta_ovl	6	4	D	6	4	128	12	-	0x7400
	LFEtaConvLUT	eta_in	eta_gmt	6	6	D	6	6	128	8	-	0x7A00
	LFMergeRankPtQ	pt, q	mrk_ptq	8	2	D	8	2	512	8	-	0x7E00
	LFPhiProEtaConvLUT	eta_in	eta_red	6	4	D	6	4	128	8	-	0x8E00
	LFSortRankEtaQLUT	eta_in, q	srk_etaq, very_low_q	9	4	B(1)	7	16	256	8	8	0x10000
	LFSortRankPtQLUT	pt, q	srk_ptq	8	7	B(1)	7	14	256	8	8	0x10800
	LFSortRankEtaPhiLUT	eta_in, phi	srk_etaphi / disable_hot	14	2	B(2)	11	16	4096	8	16	0x11000
	LFSortRankCombineLUT	srk_etaq, srk_ptq, srk_etaphi	sort_rank	11	8	B(1)	10	16	2048	8	8	0x19000
	LFDeltaEtaLUT	eta_in, eta_in	delta_eta	12	4	B(1)	10	16	2048	16	16	0x1D000
	LFPtMixLUT	pt, pt	pt	10	5	B(1)	9	10	1024	4	4	0x25000
	LFMergeRankEtaQ	eta_in, q	mrk_etaq, merge_method	9	8	B(1)	8	16	512	8	8	0x26000
	LFMergeRankEtaPhi	eta_in, phi	mrk_etaphi	14	1	B(1)	10	16	2048	8	8	0x27000
	LFMergeRankCombine	srk_etaq, srk_ptq, srk_etaphi	merge_rank	10	8	B(1)	9	16	1024	8	8	0x2B000
	LFDisableHotLUT	eta_in, phi	disable hot	14	1	B(1)	10	16	2048	4	4	0x2D000
	LFPhiProLUT	eta_red, pt, ch	delta_phi	10	9	B(1)	10	9	2048	8	8	0x2F000

* D ... distributed RAM, B ... Block RAM

Location	LUT name	change with scale change	change with alignment change	change with configurable	possible opimizations (excl. scales)	frequ. of change
MIAU FPGA	MIAUEtaConvLUT	eta-in, (eta-red)			none	rarely
	MIAUPhiPro1LUT	(eta-red), pt	muon to calo/vertex proj.		parameterization of phi projection	rarely
	MIAUPhiPro2LUT			isolation cell size phi	none	rarely
	MIAUEtaProLUT	eta-in, pt	muon to calo/vertex proj.	isolation cell size eta	parameterization of eta projection	rarely
Logic FPGA	LFSortRankEtaQLUT	eta_in, q			tuning of very-low quality candidate selection and ranking	Sometimes
	LFSortRankPtQLUT	pt, q		doOvlRPCAnd	tuning of ranking	rarely
	LFSortRankEtaPhiLUT	eta_in		list of hot regions	tuning of ranking	often (hot channels)
	LFSortRankCombineLUT				tuning of ranking	rarely
	LFDeltaEtaLUT	eta_in, (delta_eta)			none	rarely
	OvlEtaConvLUT	eta_in, (ovl_eta)			none	rarely
	LFCOUDeltaEta	(ovl_eta), (delta_eta)			none	rarely
	LFMatchQualLUT			matching windows & thresholds	tuning of matching	rarely
	LFEtaConvLUT	eta_in, eta_gmt			none	rarely
	LFMergeRankEtaQ	eta_in, q			tuning of merging	rarely
	LFMergeRankPtQ	pt, q			tuning of merging	rarely
	LFMergeRankEtaPhi	eta_in			tuning of merging	rarely
	LFMergeRankCombine				tuning of merging	rarely
	LFPtMixLUT	pt			custom pt combination	rarely
	LFDisableHotLUT	eta_in		hot regions	none	often (hot channels)
	LFPhiProEtaConvLUT	eta_in, (eta_red)	muon to vertrex proj.		none	rarely
	LFPhiProLUT	(eta_red), pt		PropagatePhi (true/false)	parameterization of phi projection	rarely

* contains SmartMIP AND/OR bit; ** contains SmartISO AND/OR bit; *** contains HaloOverwritesMatched bit

TBD: add read-only firmware ID register to each chip.

Hannes Sakulin, Feb 2005